1. Technical Field of the Invention
The present invention relates to a non-volatile memory element, and also to a fabrication process for such a memory element.
2. Description of Related Art
A known technique is to fabricate a non-volatile memory element in the form of an integrated electronic circuit of the MOS (for Metal-Oxide-Semiconductor) type, in which a value of one bit is recorded by electrical breakdown of an insulating layer of a capacitor. The binary value is then stored permanently. Such non-volatile memory elements are useful, for example, for repairing static or dynamic random access memories having high storage capacities.
The binary value 1 is recorded in such a non-volatile memory element by selecting the memory element by means of a gate voltage of an MOS transistor connected in series with the capacitor. A high electrical voltage, of around 7 V (volts), is then applied between power supply terminals of the element, so as to cause the breakdown of the insulating layer of the capacitor . The capacitor thus becomes electrically conducting. Such an operation is sometimes referred to as ‘antifuse’.
During a later operation for reading the binary value stored in the non-volatile memory element, the memory element is supplied with a voltage of around 2.5 V, in accordance with the normal power supply standards for integrated circuits of the MOS type. The memory element is again selected by the gate voltage of the transistor connected to the capacitor, and the conducting or insulating state of the capacitor is detected in order to read the binary value stored.
In order to obtain low-cost non-volatile memory elements, these are fabricated according to the normal fabrication processes for integrated circuits of the MOS type, which are designed to operate with a power supply voltage of around 2.5 V. The structure of the transistor connected to the capacitor of each non-volatile memory element then needs to be designed so that this transistor is not damaged by the high electrical voltage used to record a binary value equal to 1.
For this purpose, U.S. Pat. No. 6,421,293 (EP 1,014,447) discloses a non-volatile memory element, using CMOS technology, in which the transistor of the memory element comprises a drain region with electric field drift. Such a transistor is widely denoted as a ‘drift-MOSFET’ transistor. It allows a high electrical voltage to be applied to the memory element for recording the binary value 1, without damaging the transistor. The reason for this is that part of the high electrical voltage is consumed in the drain region by ohmic resistive effect, after the breakdown of the insulating layer of the capacitor.
However, in a memory element such as is disclosed in aforementioned patent, the drift-field drain region of the transistor and the capacitor are formed within an n-doped well. In addition, this well comprises an electrical isolation region of the STI (for Shallow Trench Isolation) type. The design rules that are necessarily used for the formation of a doping well impose that alignment margins be adhered to, notably because of the implementation of lithographic process steps. The non-volatile memory element then occupies a portion of surface of an integrated electronic circuit substrate that is significant, typically of around 10 μm2 (square micrometers). It is not therefore possible to substantially increase the integration level of the non-volatile memory element, for example in order to reduce its cost price.
A need accordingly exists for a non-volatile memory element that may be fabricated using MOS technology and that is compatible with a high level of integration.